1. Field of the Invention
The present invention relates to methods for depositing doped silicon oxide films onto the surface of an object. In particular, the present invention relates to chemical vapor deposition (CVD) and sub-atmospheric chemical vapor deposition (SACVD) methods for depositing a very high phosphorous doped silicon oxide film onto the surface of a silicon wafer.
2. Description of the Prior Art
One of the primary steps in the fabrication of modern semiconductor devices is the formation of thin films on a semiconductor substrate by chemical reaction of gasses. A process used to deposit a wide variety of metal and ceramic films onto the surface of an object, such as a silicon wafer is chemical vapor deposition, commonly referred to as “CVD.” In the fabrication of semiconductor devices, CVD is used to form numerous conductive device regions and layers in or on a semiconductor substrate. These underlying regions or layers must then be isolated and connected to form circuits and devices. To isolate these regions and areas, an interlayer dielectric is formed over those regions. Devices within the semiconductor are further isolated or separated via methods such as etching. During an etching process, layers of oxide are removed to create trenches between devices, such as via argon sputtering, for example.
Over the last several decades, circuit and device sizes within semiconductor chips have decreased dramatically. About every two years, a chip is capable of holding twice as many circuits. The dramatic decrease in size of semiconductor device geometries reduces the acceptable tolerances of circuit design and chip manufacturing. Impurities and defects can therefore, have a greater affect on chip reliability and performance. Accordingly, the quality of integrated circuits becomes highly dependant on a number of factors, including the quality of the oxide layers, the quality and precision of the etching, the quality of the doping of various layers, etc.
Referring now to FIG. 1, depicted therein is the cross-section of a common Si—SiO2 substrate within an annealed oxide stack which may be used as a semiconductor wafer upon which to embed a circuit. The Si—SiO2 substrate 100, has SiO2 regions 102, and is shown having standard oxide layers (an oxide stack) deposited thereon, such as an undoped silicon glass (USG) 108, a phosphorus doped silicon glass (phophosilicate glass or PSG) 108, and a boron and phosphorus doped silicon glass (borophophosilicate glass or BPSG) 104. An isolation trench or sub-micron hole 110 has been etched through the annealed oxide stack to the Si—SiO2 substrate 100, such as via plasma etching process, in order to form a device, such as a transistor. As shown in FIG. 1, the sub-micron hole 110 travels from above the BPSG layer 104 and is cleanly etched to the surface of the Si—SiO2 substrate, thus exposing the edges of the SiO2 regions 102. Precision and placement of sub-micron holes is extremely important to the quality of the circuits on a chip.
A common problem in semiconductor manufacturing is the under-etching of such isolation trenches. Under-etching may cause devices to fail, to be less reliable, or to perform poorly. Thus, under-etching causes manufacturing of semiconductor chips to be more costly and time consuming, since a certain number of chips must be discarded because of the aforementioned problems.
Under-etching of oxide layers may be caused by a number of factors, including the quality of the oxide layers. One of the oxide layers that significantly affects the number of sub-micron holes that are under-etched is the PSG layer between the USG layer and the BPSG layer. The PSG layer is typically formed using a CVD technique, such as sub-atmospheric CVD (SACVD), plasma enhanced CVD (PECVD), etc. and is generally deposited using a number of doped sources in conjunction with an ozone (O3) source, which allows for steady growth of a PSG layer onto a silicon wafer and has good gap filling capabilities. It has been found that by increasing the concentration of phosphorous in the PSG film, the number of under-etched sub-micron holes may be significantly reduced during the manufacture of semi-conductor chips. Current methods of depositing a PSG layer are limited in the concentration of phosphorus in the PSG layer which is produced. Accordingly, there is a need for new and improved methods for depositing very high phosphorous doped silicon oxide films in order to improve chip manufacturing, device size, chip performance and quality, etc. To be viable, such methods should take advantage of current manufacturing equipment and techniques, so they may be implemented easily and without undue burden to current and prospective manufacturers. Also, such methods should be efficient and inexpensive when compared to current methods.